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» Parallel simulation of chip-multiprocessor architectures
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TECS
2008
122views more  TECS 2008»
13 years 8 months ago
Quantitative analysis of the speed/accuracy trade-off in transaction level modeling
tion. Transaction Level Modeling (TLM) has been proposed to abstract communication for highspeed system simulation and rapid design space exploration. Although being widely accepte...
Gunar Schirner, Rainer Dömer
HPDC
2008
IEEE
14 years 2 months ago
Combining batch execution and leasing using virtual machines
As cluster computers are used for a wider range of applications, we encounter the need to deliver resources at particular times, to meet particular deadlines, and/or at the same t...
Borja Sotomayor, Kate Keahey, Ian T. Foster
IPPS
2005
IEEE
14 years 2 months ago
A Dependency Chain Clustered Microarchitecture
In this paper we explore a new clustering approach for reducing the complexity of wide issue in-order processors based on EPIC architectures. Complexity effectiveness is achieved ...
Satish Narayanasamy, Hong Wang 0003, Perry H. Wang...
CLADE
2003
IEEE
14 years 1 months ago
vGrid: A Framework For Building Autonomic Applications
With rapid technological advances in network infrastructure, programming languages, compatible component interfaces and so many more areas, today the computational Grid has evolve...
Bithika Khargharia, Salim Hariri, Manish Parashar,...
HPDC
2000
IEEE
14 years 25 days ago
QoS and Contention-Aware Multi-Resource Reservation
To provide Quality of Service (QoS) guarantee in distributed services, it is necessary to reserve multiple computing and communication resources for each service session. Meanwhile...
Dongyan Xu, Klara Nahrstedt, Arun Viswanathan, Dua...