770 search results - page 17 / 154 » Parallel simulation of chip-multiprocessor architectures |
IISWC
2009
IEEE
14 years 3 months ago
2009
IEEE
PARSEC is a reference application suite used in industry and academia to assess new Chip Multiprocessor (CMP) designs. No investigation to date has profiled PARSEC on real hardwa...
NOCS
2007
IEEE
14 years 2 months ago
2007
IEEE
Recent remarkable advances in nanoscale siliconphotonic integrated circuitry specifically compatible with CMOS fabrication have generated new opportunities for leveraging the uni...
ICDE
2009
IEEE
14 years 3 months ago
2009
IEEE
Applications involving analysis of data streams have gained significant popularity and importance. Frequency counting, frequent elements and top-k queries form a class of operato...
ASPLOS
2006
ACM
14 years 5 days ago
2006
ACM
Architects use cycle-by-cycle simulation to evaluate design choices and understand tradeoffs and interactions among design parameters. Efficiently exploring exponential-size desig...
IEEEPACT
2005
IEEE
14 years 2 months ago
2005
IEEE
In this paper we compare the performance of area equivalent small, medium, and large-scale multithreaded chip multiprocessors (CMTs) using throughput-oriented applications. We use...