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» Parallel simulation of chip-multiprocessor architectures
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ASAP
2000
IEEE
125views Hardware» more  ASAP 2000»
14 years 28 days ago
High Level Modeling for Parallel Executions of Nested Loop Algorithms
High level modeling and (quantitative) performance analysis of signal processing systems requires high level models for the applications(algorithms) and the implementations (archi...
Ed F. Deprettere, Edwin Rijpkema, Paul Lieverse, B...
ICPP
2008
IEEE
14 years 3 months ago
XMT-GPU: A PRAM Architecture for Graphics Computation
The shading processors in graphics hardware are becoming increasingly general-purpose. We test, through simulation and benchmarking, the potential performance impact of replacing ...
Thomas M. DuBois, Bryant Lee, Yi Wang, Marc Olano,...
IPPS
2008
IEEE
14 years 2 months ago
Reducing the run-time of MCMC programs by multithreading on SMP architectures
The increasing availability of multi-core and multiprocessor architectures provides new opportunities for improving the performance of many computer simulations. Markov Chain Mont...
Jonathan M. R. Byrd, Stephen A. Jarvis, A. H. Bhal...
HIPC
2007
Springer
14 years 2 months ago
Molecular Dynamics Simulations on Commodity GPUs with CUDA
Molecular dynamics simulations are a common and often repeated task in molecular biology. The need for speeding up this treatment comes from the requirement for large system simula...
Weiguo Liu, Bertil Schmidt, Gerrit Voss, Wolfgang ...
NOCS
2007
IEEE
14 years 2 months ago
Fast, Accurate and Detailed NoC Simulations
Network-on-Chip (NoC) architectures have a wide variety of parameters that can be adapted to the designer’s requirements. Fast exploration of this parameter space is only possib...
Pascal T. Wolkotte, Philip K. F. Hölzenspies,...