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» Parallel simulation of chip-multiprocessor architectures
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EUROPAR
2009
Springer
14 years 4 months ago
PSINS: An Open Source Event Tracer and Execution Simulator for MPI Applications
The size of supercomputers in numbers of processors is growing exponentially. Today’s largest supercomputers have upwards of a hundred thousand processors and tomorrow’s may ha...
Mustafa M. Tikir, Michael Laurenzano, Laura Carrin...
ISCAS
2003
IEEE
103views Hardware» more  ISCAS 2003»
14 years 3 months ago
A massively scaleable decoder architecture for low-density parity-check codes
A massively scalable architecture for decoding low-density parity-check codes is presented in this paper. This novel architecture uses hardware scaling and memory partitioning to ...
Anand Selvarathinam, Gwan Choi, Krishna Narayanan,...
IEEEPACT
2003
IEEE
14 years 3 months ago
Picking Statistically Valid and Early Simulation Points
Modern architecture research relies heavily on detailed pipeline simulation. Simulating the full execution of an industry standard benchmark can take weeks to months to complete. ...
Erez Perelman, Greg Hamerly, Brad Calder
ISPDC
2005
IEEE
14 years 3 months ago
Parallel Jess
Distributed or parallel rule-based systems are currently needed for real applications. The proposed architecture of such a system is based on a wrapper allowing the cooperation bet...
Dana Petcu
IPPS
1998
IEEE
14 years 2 months ago
A Parallel Algorithm for Minimum Cost Path Computation on Polymorphic Processor Array
This paper describes a new parallel algorithm for Minimum Cost Path computation on the Polymorphic Processor Array, a massively parallel architecture based on a reconfigurable mesh...
Pierpaolo Baglietto, Massimo Maresca, Mauro Miglia...