770 search results - page 71 / 154 » Parallel simulation of chip-multiprocessor architectures |
134
Voted
IPPS
2006
IEEE
15 years 9 months ago
2006
IEEE
In this paper, we present a dynamically reconfigurable cache architecture using adaptive block allocation policy analyzed by means of simulation. Our main objectives are: to propo...
112
Voted
VLSISP
2002
15 years 3 months ago
2002
Abstract. This paper presents a reduced-complexity, fixed-point algorithm and efficient real-time VLSI architectures for multiuser channel estimation, one of the core baseband proc...
121
Voted
HPCA
2005
IEEE
16 years 3 months ago
2005
IEEE
Due to the simulation time of the reference input set, architects often use alternative simulation techniques. Although these alternatives reduce the simulation time, what has not...
156
Voted
FCCM
2009
IEEE
15 years 7 months ago
2009
IEEE
Artificial neural networks are a key tool for researchers attempting to understand and replicate the behaviour and intelligence found in biological neural networks. Software simul...
129
Voted
PDCAT
2004
Springer
15 years 8 months ago
2004
Springer
Abstract. This paper proposes a simplified simultaneous multithreading (SMT) architecture aiming at CPU cores of embedded SoCs for consumer applications. This architecture reduces...