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» Parallel simulation of chip-multiprocessor architectures
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HPCA
2003
IEEE
16 years 3 months ago
Active I/O Switches in System Area Networks
We present an active switch architecture to improve the performance of systems connected via system area networks. Our programmable active switches not only flexibly route packets...
Ming Hao, Mark Heinrich
133
Voted
SI3D
1995
ACM
15 years 7 months ago
The Sort-First Rendering Architecture for High-Performance Graphics
Interactive graphics applications have long been challenging graphics system designers by demanding machines that can provide ever increasing polygon rendering performance. Anothe...
Carl Mueller
134
Voted
ISCA
1990
IEEE
186views Hardware» more  ISCA 1990»
15 years 7 months ago
Adaptive Software Cache Management for Distributed Shared Memory Architectures
An adaptive cache coherence mechanism exploits semantic information about the expected or observed access behavior of particular data objects. We contend that, in distributed shar...
John K. Bennett, John B. Carter, Willy Zwaenepoel
162
Voted
ICS
2004
Tsinghua U.
15 years 9 months ago
EXPERT: expedited simulation exploiting program behavior repetition
Studying program behavior is a central component in architectural designs. In this paper, we study and exploit one aspect of program behavior, the behavior repetition, to expedite...
Wei Liu, Michael C. Huang
PROCEDIA
2010
119views more  PROCEDIA 2010»
15 years 1 months ago
Performance and accuracy of Lattice-Boltzmann kernels on multi- and manycore architectures
We present different kernels based on Lattice-Boltzmann methods for the solution of the twodimensional Shallow Water and Navier-Stokes equations on fully structured lattices. The...
Dirk Ribbrock, Markus Geveler, Dominik Göddek...