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IEEEPACT
2008
IEEE
14 years 5 months ago
Leveraging on-chip networks for data cache migration in chip multiprocessors
Recently, chip multiprocessors (CMPs) have arisen as the de facto design for modern high-performance processors, with increasing core counts. An important property of CMPs is that...
Noel Eisley, Li-Shiuan Peh, Li Shang
WSC
2001
14 years 5 days ago
Managing event traces for a web front-end to a parallel simulation
To enhance the widespread use of a parallel supply chain simulator, a web front-end that enables access at any time and from any location has been developed. The front-end provide...
Boon-Ping Gan, Li Liu, Zhengrong Ji, Stephen John ...
IPPS
1999
IEEE
14 years 3 months ago
A Communication Latency Hiding Parallelization of a Traffic Flow Simulation
This work implements and analyses a highway traffic flow simulation based on continuum modeling of traffic dynamics. A traffic-flow simulation was developed and mapped onto a para...
Charles Michael Johnston, Anthony T. Chronopoulos
PPOPP
1990
ACM
14 years 2 months ago
Multi-Model Parallel Programming in Psyche
Many different parallel programming models, including lightweight processes that communicate with shared memory and heavyweight processes that communicate with messages, have been...
Michael L. Scott, Thomas J. LeBlanc, Brian D. Mars...
ISSS
2002
IEEE
125views Hardware» more  ISSS 2002»
14 years 3 months ago
Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...
Satoshi Matsushita