1761 search results - page 59 / 353 » Parallel timing simulation on a distributed memory multiproc... |
IPPS
2002
IEEE
14 years 3 months ago
2002
IEEE
We present a parallel algorithm for performing multipoint linkage analysis of genetic marker data on large family pedigrees. The algorithm effectively distributes both the computa...
DAC
2010
ACM
13 years 10 months ago
2010
ACM
We present RAMP Gold, an economical FPGA-based architecture simulator that allows rapid early design-space exploration of manycore systems. The RAMP Gold prototype is a high-throu...
CJ
2006
13 years 10 months ago
2006
Most microprocessor chips today use an out-of-order instruction execution mechanism. This mechanism allows superscalar processors to extract reasonably high levels of instruction ...
IEEEPACT
2005
IEEE
14 years 4 months ago
2005
IEEE
Transactional Coherence and Consistency (TCC) is a novel coherence scheme for shared memory multiprocessors that uses programmer-defined transactions as the fundamental unit of p...
IAJIT
2011
13 years 5 months ago
2011
: The present paper discusses the implementations of sparse matrix-vector products, which are crucial for high performance solutions of large-scale linear equations, on a PC-Cluste...