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CORR
2006
Springer
112views Education» more  CORR 2006»
13 years 8 months ago
High-level synthesis under I/O Timing and Memory constraints
The design of complex Systems-on-Chips implies to take into account communication and memory access constraints for the integration of dedicated hardware accelerator. In this paper...
Philippe Coussy, Gwenolé Corre, Pierre Bome...
CCGRID
2009
IEEE
14 years 19 days ago
Flexible and Efficient In-Vivo Enhancement for Grid Applications
In a grid application, some requirements may change while the execution is in progress. This paper presents invivo enhancement
Dong Kwan Kim, Yang Jiao, Eli Tilevich
COREGRID
2007
Springer
14 years 2 months ago
Optimal Closest Policy with Qos and Bandwidth Constraints
This paper deals with the replica placement problem on fully homogeneous tree networksknownasthe Replica Placementoptimizationproblem. Theclient requests are known beforehand, whil...
Veronika Rehn-Sonigo
ISCAS
2005
IEEE
123views Hardware» more  ISCAS 2005»
14 years 2 months ago
Sub-operation parallelism optimization in SIMD processor synthesis and its experimental evaluations
Abstract— In this paper, we propose a sub-operation parallelism optimization algorithm in SIMD processor synthesis. Given an initial assembly code and timing constraints, our alg...
Nozomu Togawa, Hideki Kawazu, Jumpei Uchida, Yuich...
PPDP
2005
Springer
14 years 2 months ago
Heuristics, optimizations, and parallelism for protein structure prediction in CLP(FD)
The paper describes a constraint-based solution to the protein folding problem on face-centered cubic lattices—a biologically meaningful approximation of the general protein fol...
Alessandro Dal Palù, Agostino Dovier, Enric...