Sciweavers

7456 search results - page 1402 / 1492
» Parallelism in Logic Programs
Sort
View
ICCD
1999
IEEE
110views Hardware» more  ICCD 1999»
14 years 2 months ago
TriMedia CPU64 Architecture
We present a new VLIW core as a successor to the TriMedia TM1000. The processor is targeted for embedded use in media-processing devices like DTVs and set-top boxes. Intended as a...
Jos T. J. van Eijndhoven, Kees A. Vissers, Evert-J...
IV
1999
IEEE
91views Visualization» more  IV 1999»
14 years 2 months ago
Triangle Mesh Compression for Fast Rendering
Modern GIS(Geographic Information System) application programs and simulation systems have to handle large datasets for rendering. Currently three dimensional rendering hardware a...
Dong-Gyu Park, Yang-Soo Kim, Hwan-Gue Cho
MICRO
1998
IEEE
98views Hardware» more  MICRO 1998»
14 years 2 months ago
Task Selection for a Multiscalar Processor
The Multiscalar architecture advocates a distributed processor organization and task-level speculation to exploit high degrees of instruction level parallelism (ILP) in sequential...
T. N. Vijaykumar, Gurindar S. Sohi
VLDB
1998
ACM
102views Database» more  VLDB 1998»
14 years 2 months ago
A Database System for Real-Time Event Aggregation in Telecommunication
Telecommunication networks process verylarge numbers of events in real time. In this environment, database applications demand both high throughput (at reasonable costs), and pred...
Jerry Baulier, Stephen Blott, Henry F. Korth, Abra...
MICRO
1997
IEEE
76views Hardware» more  MICRO 1997»
14 years 2 months ago
A Framework for Balancing Control Flow and Predication
Predicated execution is a promising architectural feature for exploiting instruction-level parallelism in the presence of control flow. Compiling for predicated execution involve...
David I. August, Wen-mei W. Hwu, Scott A. Mahlke
« Prev « First page 1402 / 1492 Last » Next »