26 search results - page 2 / 6 » Parallelization in Co-Compilation for Configurable Accelerat... |
SIGARCH
2010
13 years 2 months ago
2010
We describe a programming framework for high performance clusters with various hardware accelerators. In this framework, users can utilize the available heterogeneous resources pr...
CORR
2008
Springer
13 years 7 months ago
2008
Springer
In piezoresisitive two-axis accelerometers with two proof masses suspended by cantilever beams, there are generally many ways to configure the Wheatstone bridges. The configuratio...
IPPS
2007
IEEE
14 years 1 months ago
2007
IEEE
The Xilinx Virtex family of FPGAs provides the ability to perform partial run-time reconfiguration, also known as dynamic partial reconfiguration (DPR). Taking this concept one st...
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
We propose an interleaved memory organization supporting multi-pattern parallel accesses in twodimensional (2D) addressing space. Our proposal targets computing systems with high ...
MICRO
2010
IEEE
13 years 5 months ago
2010
IEEE
This paper presents ReMAP, a reconfigurable architecture geared towards accelerating and parallelizing applications within a heterogeneous CMP. In ReMAP, threads share a common rec...