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ICPADS
2010
IEEE
13 years 5 months ago
Enhancing MapReduce via Asynchronous Data Processing
The MapReduce programming model simplifies large-scale data processing on commodity clusters by having users specify a map function that processes input key/value pairs to generate...
Marwa Elteir, Heshan Lin, Wu-chun Feng
IPPS
2010
IEEE
13 years 5 months ago
Adapting cache partitioning algorithms to pseudo-LRU replacement policies
Abstract-- Recent studies have shown that cache partitioning is an efficient technique to improve throughput, fairness and Quality of Service (QoS) in CMP processors. The cache par...
Kamil Kedzierski, Miquel Moretó, Francisco ...
SPAA
2004
ACM
14 years 24 days ago
Cache-oblivious shortest paths in graphs using buffer heap
We present the Buffer Heap (BH), a cache-oblivious priority queue that supports Delete-Min, Delete, and Decrease-Key operations in O( 1 B log2 N B ) amortized block transfers fro...
Rezaul Alam Chowdhury, Vijaya Ramachandran
HPCA
2009
IEEE
14 years 8 months ago
Prediction router: Yet another low latency on-chip router architecture
Network-on-Chips (NoCs) are quite latency sensitive, since their communication latency strongly affects the application performance on recent many-core architectures. To reduce th...
Hiroki Matsutani, Michihiro Koibuchi, Hideharu Ama...
HPCA
2009
IEEE
14 years 8 months ago
Versatile prediction and fast estimation of Architectural Vulnerability Factor from processor performance metrics
The shrinking processor feature size, lower threshold voltage and increasing clock frequency make modern processors highly vulnerable to transient faults. Architectural Vulnerabil...
Lide Duan, Bin Li, Lu Peng