47 search results - page 7 / 10 » Parallelizing HMMER for Hardware Acceleration on FPGAs |
TVLSI
2008
13 years 7 months ago
2008
Most hardware compilers apply loop pipelining to increase the parallelism achieved, but pipelining is restricted to the only innermost level in a nested loop. In this work we exten...
SASP
2009
IEEE
14 years 2 months ago
2009
IEEE
— As growing power dissipation and thermal effects disrupted the rising clock frequency trend and threatened to annul Moore’s law, the computing industry has switched its route...
ENGL
2008
13 years 8 months ago
2008
High performance computing is becoming increasingly important in the field of financial computing, as the complexity of financial models continues to increase. Many of these financ...
ISPAN
2005
IEEE
14 years 1 months ago
2005
IEEE
Within the parallel computing domain, field programmable gate arrays (FPGA) are no longer restricted to their traditional role as substitutes for application-specific integrated...
FPGA
2010
ACM
14 years 1 months ago
2010
ACM
This paper describes a heterogeneous computer cluster called Axel. Axel contains a collection of nodes; each node can include multiple types of accelerators such as FPGAs (Field P...