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IPPS
2010
IEEE
13 years 4 months ago
Restructuring parallel loops to curb false sharing on multicore architectures
The memory hierarchy of most multicore systems contains one or more levels of cache that is shared among multiple cores. The shared-cache architecture presents many opportunities f...
Santosh Sarangkar, Apan Qasem
ISCAS
2005
IEEE
124views Hardware» more  ISCAS 2005»
14 years 9 days ago
Parallel FFT computation with a CDMA-based network-on-chip
— Fast Fourier transform (FFT) algorithms are used in a wide variety of digital signal processing applications and many of these require high-performance parallel implementations...
Daewook Kim, Manho Kim, Gerald E. Sobelman
TROB
2002
120views more  TROB 2002»
13 years 6 months ago
DPAC: an object-oriented distributed and parallel computing framework for manufacturing applications
Parallel and distributed computing infrastructure are increasingly being embraced in the context of manufacturing applications, including real-time scheduling. In this paper, we pr...
N. R. Srinivasa Raghavan, Tanmay Waghmare
ICCS
2001
Springer
13 years 11 months ago
On the Effectiveness of D-BSP as a Bridging Model of Parallel Computation
This paper surveys and places into perspective a number of results concerning the D-BSP (Decomposable Bulk Synchronous Parallel) model of computation, a variant of the popular BSP ...
Gianfranco Bilardi, Carlo Fantozzi, Andrea Pietrac...
IPPS
2000
IEEE
13 years 11 months ago
Fast Measurement of LogP Parameters for Message Passing Platforms
Abstract. Performance modeling is important for implementing efficient parallel applications and runtime systems. The LogP model captures the relevant aspects of message passing i...
Thilo Kielmann, Henri E. Bal, Kees Verstoep