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ISCA
2005
IEEE
144views Hardware» more  ISCA 2005»
14 years 1 months ago
Scalable Load and Store Processing in Latency Tolerant Processors
Memory latency tolerant architectures support thousands of in-flight instructions without scaling cyclecritical processor resources, and thousands of useful instructions can compl...
Amit Gandhi, Haitham Akkary, Ravi Rajwar, Srikanth...
ICS
2005
Tsinghua U.
14 years 1 months ago
Disk layout optimization for reducing energy consumption
Excessive power consumption is becoming a major barrier to extracting the maximum performance from high-performance parallel systems. Therefore, techniques oriented towards reduci...
Seung Woo Son, Guangyu Chen, Mahmut T. Kandemir
COORDINATION
2004
Springer
14 years 1 months ago
Active Coordination in Ad Hoc Networks
The increasing ubiquity of mobile devices has led to an explosion in the development of applications tailored to the particular needs of individual users. As the research communit...
Christine Julien, Gruia-Catalin Roman
FPGA
2004
ACM
119views FPGA» more  FPGA 2004»
14 years 1 months ago
A quantitative analysis of the speedup factors of FPGAs over processors
The speedup over a microprocessor that can be achieved by implementing some programs on an FPGA has been extensively reported. This paper presents an analysis, both quantitative a...
Zhi Guo, Walid A. Najjar, Frank Vahid, Kees A. Vis...
ICPP
2003
IEEE
14 years 1 months ago
Data Conversion for Process/Thread Migration and Checkpointing
Process/thread migration and checkpointing schemes support load balancing, load sharing and fault tolerance to improve application performance and system resource usage on worksta...
Hai Jiang, Vipin Chaudhary, John Paul Walters
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