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IEEEPACT
2005
IEEE
14 years 1 months ago
Future Execution: A Hardware Prefetching Technique for Chip Multiprocessors
This paper proposes a new hardware technique for using one core of a CMP to prefetch data for a thread running on another core. Our approach simply executes a copy of all non-cont...
Ilya Ganusov, Martin Burtscher
ISCAS
2005
IEEE
103views Hardware» more  ISCAS 2005»
14 years 1 months ago
Why area might reduce power in nanoscale CMOS
— In this paper we explore the relationship between power and area. By exploiting parallelism (and thus using more area) one can reduce the switching frequency allowing a reducti...
Paul Beckett, S. C. Goldstein
ISESE
2005
IEEE
14 years 1 months ago
Empirical study design in the area of high-performance computing (HPC)
The development of High-Performance Computing (HPC) programs is crucial to progress in many fields of scientific endeavor. We have run initial studies of the productivity of HPC d...
Forrest Shull, Jeffrey Carver, Lorin Hochstein, Vi...
SKG
2005
IEEE
14 years 1 months ago
Converting the Industry Foundation Classes to the Web Ontology Language
The upcoming next generation of the internet, often referred to as the Semantic Web, will bring a lot of new technologies, one of which is the Web Ontology Language (OWL). One fea...
Hans Schevers, Robin Drogemuller
SC
2005
ACM
14 years 1 months ago
Making Sequential Consistency Practical in Titanium
The memory consistency model in parallel programming controls the order in which operations performed by one thread may be observed by another. Language designers have been reluct...
Amir Kamil, Jimmy Su, Katherine A. Yelick
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