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ICPADS
2006
IEEE
14 years 2 months ago
Loop Scheduling with Complete Memory Latency Hiding on Multi-core Architecture
The widening gap between processor and memory performance is the main bottleneck for modern computer systems to achieve high processor utilization. In this paper, we propose a new...
Chun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edw...
ISCAS
2006
IEEE
119views Hardware» more  ISCAS 2006»
14 years 2 months ago
Performance improvement of the H.264/AVC deblocking filter using SIMD instructions
The H.264/AVC standard defines an in-loop de- instructions, available in current multimedia SIMD instruction blocking filter which is used in both the encoder and decoder. This set...
Stephen Warrington, Hassan Shojania, Subramania Su...
ISORC
2006
IEEE
14 years 2 months ago
JAAT: Java Alias Analysis Tool for Program Maintenance Activities
Alias analysis is a method for extracting sets of expressions which may possibly refer to the same memory locations during program execution. Although many researchers have alread...
Fumiaki Ohata, Katsuro Inoue
CASES
2006
ACM
14 years 2 months ago
High-level languages for small devices: a case study
In this paper we study, through a concrete case, the feasibility of using a high-level, general-purpose logic language in the design and implementation of applications targeting w...
Manuel Carro, José F. Morales, Henk L. Mull...
IWCMC
2006
ACM
14 years 2 months ago
Budgeting power: packet duplication and bit error rate reduction in wireless ad-hoc networks
In this paper we present and evaluate a new technique to lower packet-level error rates of application layer connections in wireless ad-hoc networks. In our scheme, data packets s...
Ghassen Ben Brahim, Bilal Khan
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