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ISVLSI
2005
IEEE
169views VLSI» more  ISVLSI 2005»
14 years 3 months ago
High Performance Array Processor for Video Decoding
high NRE cost. Therefore, general purpose programmable processors using software to perform various functions become more attractive since programmability can simplify system devel...
J. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin
PODC
2005
ACM
14 years 3 months ago
Quorum placement in networks to minimize access delays
A quorum system is a family of sets (themselves called quorums), each pair of which intersect. In many distributed algorithms, the basic unit accessed by a client is a quorum of n...
Anupam Gupta, Bruce M. Maggs, Florian Oprea, Micha...
ISLPED
2004
ACM
137views Hardware» more  ISLPED 2004»
14 years 3 months ago
Location cache: a low-power L2 cache system
While set-associative caches incur fewer misses than directmapped caches, they typically have slower hit times and higher power consumption, when multiple tag and data banks are p...
Rui Min, Wen-Ben Jone, Yiming Hu
ICS
2004
Tsinghua U.
14 years 3 months ago
Scaling the issue window with look-ahead latency prediction
In contemporary out-of-order superscalar design, high IPC is mainly achieved by exposing high instruction level parallelism (ILP). Scaling issue window size can certainly provide ...
Yongxiang Liu, Anahita Shayesteh, Gokhan Memik, Gl...
SAG
2004
Springer
14 years 3 months ago
A Framework for the Design and Reuse of Grid Workflows
Grid workflows can be seen as special scientific workflows involving high performance and/or high throughput computational tasks. Much work in grid workflows has focused on improvi...
Ilkay Altintas, Adam Birnbaum, Kim Baldridge, Wibk...