356 search results - page 11 / 72 » Parallelizing time with polynomial circuits |
IJFCS
2008
13 years 8 months ago
2008
We propose two different ways to simulate Boolean circuits in the framework of ciliate computations, based on the intramolecular and on the intermolecular gene assembly models wit...
STACS
2010
Springer
14 years 2 months ago
2010
Springer
Kabanets and Impagliazzo [KI04] show how to decide the circuit polynomial identity testing problem (CPIT) in deterministic subexponential time, assuming hardness of some explicit ...
CSL
2007
Springer
14 years 2 months ago
2007
Springer
Abstract. By introducing a parallel extension rule that is aware of independence of the introduced extension variables, a calculus for quantified propositional logic is obtained w...
DAC
2005
ACM
13 years 9 months ago
2005
ACM
Capturing RLCK circuit responses accurately with existing model order reduction (MOR) techniques is very expensive. Direct metrics for fast analysis of RC circuits exist but there...
DAC
1999
ACM
14 years 6 days ago
1999
ACM
: In this work we propose a technique for spatial and temporal partitioning of a logic circuit based on the nodes activity computed by using a simulation at an higher level of ion....