149 search results - page 21 / 30 » Parametric Fault Simulation and Test Vector Generation |
VTS
1997
IEEE
13 years 11 months ago
1997
IEEE
Accumulators based on addition or subtraction can be used as test pattern generators. Some circuits, however, require long test lengths if the parameters of the accumulator are no...
DAC
1997
ACM
13 years 11 months ago
1997
ACM
This paper presents a new scan-based BIST scheme which achieves very high fault coverage without the deficiencies of previously proposed schemes. This approach utilizes scan order...
CAD
2005
Springer
13 years 7 months ago
2005
Springer
In 3-axis NC (Numerical Control) machining, various cutters are used and the offset compensation for these cutters is important for a gouge free tool path generation. This paper i...
ASYNC
2000
IEEE
13 years 11 months ago
2000
IEEE
Fault Abstraction and Collapsing Framework for Asynchronous Circuits Philip P. Shirvani, Subhasish Mitra Center for Reliable Computing Stanford University Stanford, CA Jo C. Eberge...
ICCAD
2000
IEEE
13 years 11 months ago
2000
IEEE
We present an error catch and analysis (ECA) system for semiconductor memories. The system consists of a test algorithm generator called TAGS, a fault simulator called RAMSES, and...