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» Partial Order Reductions for Bisimulation Checking
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FMSD
2002
128views more  FMSD 2002»
13 years 7 months ago
Combining Software and Hardware Verification Techniques
Combining verification methods developed separately for software and hardware is motivated by the industry's need for a technology that would make formal verification of reali...
Robert P. Kurshan, Vladimir Levin, Marius Minea, D...
DATE
2004
IEEE
184views Hardware» more  DATE 2004»
13 years 11 months ago
Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB Refinements
We show how to automatically verify that complex XScale-like pipelined machine models satisfy the same safety and liveness properties as their corresponding instruction set archit...
Panagiotis Manolios, Sudarshan K. Srinivasan
SPIN
2000
Springer
13 years 11 months ago
Model Checking Based on Simultaneous Reachability Analysis
Abstract. Simultaneous reachability analysis SRA is a recently proposed approach to alleviating the state space explosion problem in reachability analysis of concurrent systems. Th...
Bengi Karaçali, Kuo-Chung Tai
ATVA
2008
Springer
131views Hardware» more  ATVA 2008»
13 years 9 months ago
Dynamic Model Checking with Property Driven Pruning to Detect Race Conditions
We present a new property driven pruning algorithm in dynamic model checking to efficiently detect race conditions in multithreaded programs. The main idea is to use a lockset base...
Chao Wang, Yu Yang, Aarti Gupta, Ganesh Gopalakris...
TACAS
2010
Springer
181views Algorithms» more  TACAS 2010»
14 years 2 months ago
Boom: Taking Boolean Program Model Checking One Step Further
Abstract. We present Boom, a comprehensive analysis tool for Boolean programs. We focus in this paper on model-checking non-recursive concurrent programs. Boom implements a recent ...
Gérard Basler, Matthew Hague, Daniel Kroeni...