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ICSE
2004
IEEE-ACM
14 years 8 months ago
The Dublo Architecture Pattern for Smooth Migration of Business Information Systems: An Experience Report
While the importance of multi-tier architectures for enterprise information systems is widely accepted and their benefits are well published, the systematic migration from monolit...
Wilhelm Hasselbring, Ralf Reussner, Holger Jaekel,...
ICCD
2002
IEEE
98views Hardware» more  ICCD 2002»
14 years 5 months ago
Parallel Multiple-Symbol Variable-Length Decoding
In this paper, a parallel Variable-Length Decoding (VLD) scheme is introduced. The scheme is capable of decoding all the codewords in an N-bit buffer whose accumulated codelength ...
Jari Nikara, Stamatis Vassiliadis, Jarmo Takala, M...
ATS
2009
IEEE
142views Hardware» more  ATS 2009»
14 years 3 months ago
Speeding up SAT-Based ATPG Using Dynamic Clause Activation
Abstract—SAT-based ATPG turned out to be a robust alternative to classical structural ATPG algorithms such as FAN. The number of unclassified faults can be significantly reduce...
Stephan Eggersglüß, Daniel Tille, Rolf ...
IPPS
2009
IEEE
14 years 3 months ago
High-level estimation and trade-off analysis for adaptive real-time systems
We propose a novel design estimation method for adaptive streaming applications to be implemented on a partially reconfigurable FPGA. Based on experimental results we enable accu...
Ingo Sander, Jun Zhu, Axel Jantsch, Andreas Herrho...
ICFEM
2009
Springer
14 years 3 months ago
Scalable Multi-core Model Checking Fairness Enhanced Systems
Rapid development in hardware industry has brought the prevalence of multi-core systems with shared-memory, which enabled the speedup of various tasks by using parallel algorithms....
Yang Liu 0003, Jun Sun 0001, Jin Song Dong