367 search results - page 46 / 74 » Partial evaluation of machine code |
CODES
2004
IEEE
14 years 1 months ago
2004
IEEE
Register bypassing is a powerful and widely used feature in modern processors to eliminate certain data hazards. Although complete bypassing is ideal for performance, bypassing ha...
MTA
2007
13 years 9 months ago
2007
This paper describes novel transcoding techniques aimed for low-complexity MPEG-2 to H.264/AVC transcoding. An important application for this type of conversion is efficient stor...
ICFP
1998
ACM
14 years 2 months ago
1998
ACM
We present a purely functional implementation of the computational differentiation tools — the well known numeric (i.e., not symbolic) techniques which permit one to compute poin...
ICS
1995
Tsinghua U.
14 years 1 months ago
1995
Tsinghua U.
Modulo scheduling is an e cient technique for exploiting instruction level parallelism in a variety of loops, resulting in high performance code but increased register requirement...
CGO
2008
IEEE
14 years 4 months ago
2008
IEEE
Vector-thread (VT) architectures exploit multiple forms of parallelism simultaneously. This paper describes a compiler for the Scale VT architecture, which takes advantage of the ...