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» Partitioning of VLSI Circuits and Systems
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ISCAS
2008
IEEE
136views Hardware» more  ISCAS 2008»
14 years 1 months ago
VLSI architecture for data-reduced steering matrix feedback in MIMO systems
Abstract— Beamforming (BF) for multiple-input multipleoutput (MIMO) wireless communications systems can improve the error rate performance by spatial separation of the transmitte...
Christoph Studer, Peter Luethi, Wolfgang Fichtner
POPL
2007
ACM
14 years 7 months ago
Geometry of synthesis: a structured approach to VLSI design
We propose a new technique for hardware synthesis from higherorder functional languages with imperative features based on Reynolds's Syntactic Control of Interference. The re...
Dan R. Ghica
ICRA
2000
IEEE
106views Robotics» more  ICRA 2000»
13 years 11 months ago
Toward Biomorphic Control Using Custom aVLSI CPG Chips
The locomotor controller for walking, running, swimming, and flying animals is based on a Central Pattern Generator (CPG). Models of CPGs as systems of coupled non-linear oscillato...
M. Anthony Lewis, Ralph Etienne-Cummings, Avis H. ...
ISCAS
2005
IEEE
119views Hardware» more  ISCAS 2005»
14 years 1 months ago
Analysis of power consumption in VLSI global interconnects
Abstract— The analysis of effects induced by interconnects become increasingly important as the scale of process technologies steadily shrinks. While most analyses focus on the t...
Youngsoo Shin, Hyung-Ock Kim
VLSID
2003
IEEE
167views VLSI» more  VLSID 2003»
14 years 7 months ago
Timing Minimization by Statistical Timing hMetis-based Partitioning
In this paper we present statistical timing driven hMetisbased partitioning. We approach timing driven partitioning from a different perspective: we use the statistical timing cri...
Cristinel Ababei, Kia Bazargan