JHDL is a design tool for reconfigurable systems that allows designers to express circuit organizations that dynamically change over time in a natural way, using only standard pro...
This paper presents an efficient modeling scheme and a partitioning heuristic for parallelizing VLSI post-placement timing optimization. Encoding the paths with timing violations...
The presence of fixed terminals in hypergraph partitioning instances arising in top-down standard-cell placement makes such instances qualitatively different from the free hyperg...
Charles J. Alpert, Andrew E. Caldwell, Andrew B. K...
We describe an analog-VLSI neural network for face recognition based on subspace methods. The system uses a dimensionality-reduction network whose coefficients can be either progr...
Gonzalo Carvajal, Waldo Valenzuela, Miguel Figuero...
This paper presents the hardware realization of a Hamming artificial neural network, and demonstrates its use in a high-speed precision alignment system. High degree of parallelism...