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» Partitioning of VLSI Circuits and Systems
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FCCM
1998
IEEE
148views VLSI» more  FCCM 1998»
15 years 10 months ago
JHDL - An HDL for Reconfigurable Systems
JHDL is a design tool for reconfigurable systems that allows designers to express circuit organizations that dynamically change over time in a natural way, using only standard pro...
Peter Bellows, Brad L. Hutchings
IPPS
2006
IEEE
15 years 11 months ago
Parallelizing post-placement timing optimization
This paper presents an efficient modeling scheme and a partitioning heuristic for parallelizing VLSI post-placement timing optimization. Encoding the paths with timing violations...
Jiyoun Kim, Marios C. Papaefthymiou, José N...
ISPD
1999
ACM
79views Hardware» more  ISPD 1999»
15 years 10 months ago
Partitioning with terminals: a "new" problem and new benchmarks
The presence of fixed terminals in hypergraph partitioning instances arising in top-down standard-cell placement makes such instances qualitatively different from the free hyperg...
Charles J. Alpert, Andrew E. Caldwell, Andrew B. K...
NIPS
2007
15 years 7 months ago
Subspace-Based Face Recognition in Analog VLSI
We describe an analog-VLSI neural network for face recognition based on subspace methods. The system uses a dimensionality-reduction network whose coefficients can be either progr...
Gonzalo Carvajal, Waldo Valenzuela, Miguel Figuero...
ESANN
2003
15 years 7 months ago
VLSI Realization of a Two-Dimensional Hamming Distance Comparator ANN for Image Processing Applications
This paper presents the hardware realization of a Hamming artificial neural network, and demonstrates its use in a high-speed precision alignment system. High degree of parallelism...
Stéphane Badel, Alexandre Schmid, Yusuf Leb...