Sciweavers

338 search results - page 58 / 68
» Partitioning of VLSI Circuits and Systems
Sort
View
ITC
1999
IEEE
107views Hardware» more  ITC 1999»
13 years 11 months ago
A high-level BIST synthesis method based on a region-wise heuristic for an integer linear programming
A high-level built-in self-test (BIST) synthesis involves several tasks such as system register assignment, interconnection assignment, and BIST register assignment. Existing high...
Han Bin Kim, Dong Sam Ha
VLSID
2007
IEEE
130views VLSI» more  VLSID 2007»
14 years 7 months ago
Impact of NBTI on FPGAs
Device scaling such as reduced oxide thickness and high electric field has given rise to various reliability concerns. One such growing issue of concern is the degradation of PMOS...
Krishnan Ramakrishnan, S. Suresh, Narayanan Vijayk...
DFT
2008
IEEE
120views VLSI» more  DFT 2008»
14 years 1 months ago
Built-in-Self-Diagnostics for a NoC-Based Reconfigurable IC for Dependable Beamforming Applications
Integrated circuits (IC) targeting at the streaming applications for tomorrow are becoming a fast growing market. Applications such as beamforming require mass computing capabilit...
Oscar Kuiken, Xiao Zhang, Hans G. Kerkhoff
ASPDAC
2007
ACM
129views Hardware» more  ASPDAC 2007»
13 years 11 months ago
ECO-system: Embracing the Change in Placement
In a realistic design flow, circuit and system optimizations must interact with physical aspects of the design. For example, improvements in timing and power may require replacing ...
Jarrod A. Roy, Igor L. Markov
ENGL
2008
118views more  ENGL 2008»
13 years 7 months ago
Hybrid Architecture of Genetic Algorithm and Simulated Annealing
This paper discusses novel dedicated hardware architecture for hybrid optimization based on Genetic algorithm (GA) and Simulated Annealing (SA). The proposed architecture achieves ...
Masaya Yoshikawa, Hironori Yamauchi, Hidekazu Tera...