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» Partitioning of VLSI Circuits and Systems
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ISCAS
2003
IEEE
106views Hardware» more  ISCAS 2003»
14 years 20 days ago
A neuromorphic sound localizer for a smart MEMS system
In this paper we present an analog circuit that determines the direction of incoming sound using two microphones. The circuit is inspired by biology and uses two silicon cochlea to...
André van Schaik, Shihab Shamma
IPPS
2002
IEEE
14 years 10 days ago
Fast Inductance Extraction of Large VLSI Circuits
Accurate estimation of signal delay is critical to the design and verification of VLSI circuits. At very high frequencies, signal delay in circuits with small feature sizes is do...
Hemant Mahawar, Vivek Sarin, Weiping Shi
EAAI
2007
103views more  EAAI 2007»
13 years 7 months ago
Particle swarm-based optimal partitioning algorithm for combinational CMOS circuits
This paper presents a swarm intelligence based approach to optimally partition combinational CMOS circuits for pseudoexhaustive testing. The partitioning algorithm ensures reducti...
Ganesh K. Venayagamoorthy, Scott C. Smith, Gaurav ...
DFT
2005
IEEE
64views VLSI» more  DFT 2005»
14 years 1 months ago
Implementation of Concurrent Checking Circuits by Independent Sub-circuits
The present paper proposes a new method for detecting arbitrary faults in a functional circuit when the set of codewords is limited and known in advance. The method is based on im...
Vladimir Ostrovsky, Ilya Levin
ISPD
1997
ACM
142views Hardware» more  ISPD 1997»
13 years 11 months ago
Minimization of chip size and power consumption of high-speed VLSI buffers
In this paper, we study optimal bu er design in high-performance VLSI systems. Speci cally, we design a bu er for a given load such that chip area and power dissipation are minima...
D. Zhou, X. Y. Liu