This paper addresses the general single-machine earliness-tardiness problem with distinct release dates, due dates, and unit costs. The aim of this research is to obtain an exact n...
We present an efficient optimization scheme for gate sizing in the presence of process variations. Our method is a worst-case design scheme, but it reduces the pessimism involved i...
Jaskirat Singh, Zhi-Quan Luo, Sachin S. Sapatnekar
Abstract--Simplifying a combinational circuit while preserving its range has a variety of applications, such as combinational equivalence checking and random simulation. Previous a...
Background: High throughput microarray analyses result in many differentially expressed genes that are potentially responsible for the biological process of interest. In order to ...
Blaise T. F. Alako, Antoine Veldhoven, Sjozef van ...
Background: Searching for approximate patterns in large promoter sequences frequently produces an exceedingly high numbers of results. Our aim was to exploit biological knowledge ...
Stefania Bortoluzzi, Alessandro Coppe, Andrea Biso...