A Geometric Programming-Based Worst Case Gate Sizing Method Incorporating Spatial Correlation

We present an efficient optimization scheme for gate sizing in the presence of process variations. Our method is a worst-case design scheme, but it reduces the pessimism involved in traditional worst-casing methods by incorporating the effect of spatial correlations in the optimization procedure. The pessimism reduction is achieved by employing a bounded model for the parameter variations, in the form of an uncertainty ellipsoid, which captures the spatial correlation information between the physical parameters. The use of the uncertainty ellipsoid, along with the assumption that the random variables, corresponding to the varying parameters, follow a multivariate Gaussian distribution, enables us to size the circuits for a specified timing yield. Using a posynomial delay model, the delay constraints are modified to incorporate uncertainty in the transistor widths and effective channel lengths due to the process variations. The resulting optimization problem is relaxed to a Geometric Pr...

• Type: Journal
• Year: 2008
• Where: TCAD
• Authors: Jaskirat Singh, Zhi-Quan Luo, Sachin S. Sapatnekar
• Keywords: Efficient Optimization Scheme, Process Variations, Spatial Correlation, TCAD 2008