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VTS
2002
IEEE
120views Hardware» more  VTS 2002»
14 years 22 days ago
Software-Based Weighted Random Testing for IP Cores in Bus-Based Programmable SoCs
We present a software-based weighted random pattern scheme for testing delay faults in IP cores of programmable SoCs. We describe a method for determining static and transition pr...
Madhu K. Iyer, Kwang-Ting Cheng
ITC
2002
IEEE
81views Hardware» more  ITC 2002»
14 years 22 days ago
Design Rewiring Using ATPG
—Logic optimization is the step of the very large scale integration (VLSI) design cycle where the designer performs modifications on a design to satisfy different constraints suc...
Andreas G. Veneris, Magdy S. Abadir, Mandana Amiri
ECCV
2004
Springer
14 years 1 months ago
Hand Pose Estimation Using Hierarchical Detection
This paper presents an analysis of the design of classifiers for use in a hierarchical object recognition approach. In this approach, a cascade of classifiers is arranged in a tr...
Bjoern Stenger, Arasanathan Thayananthan, Philip H...
AAAI
2004
13 years 9 months ago
Analogical Path Planning
We present a probabilistic method for path planning that considers trajectories constrained by both the environment and an ensemble of restrictions or preferences on preferred mot...
Saul Simhon, Gregory Dudek
BMCBI
2008
128views more  BMCBI 2008»
13 years 8 months ago
Meta-analysis of breast cancer microarray studies in conjunction with conserved cis-elements suggest patterns for coordinate reg
Background: Gene expression measurements from breast cancer (BrCa) tumors are established clinical predictive tools to identify tumor subtypes, identify patients showing poor/good...
David D. Smith, Pål Sætrom, Ola R. Sn&...