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VLSID
2007
IEEE
104views VLSI» more  VLSID 2007»
16 years 4 months ago
Customization of Register File Banking Architecture for Low Power
Register file banking is an effective alternative to monolithic register files in embedded processor based systems. In this work, we propose techniques for performing application s...
Rakesh Nalluri, Rohan Garg, Preeti Ranjan Panda
SP
2008
IEEE
134views Security Privacy» more  SP 2008»
15 years 10 months ago
Lares: An Architecture for Secure Active Monitoring Using Virtualization
Host-based security tools such as anti-virus and intrusion detection systems are not adequately protected on today’s computers. Malware is often designed to immediately disable ...
Bryan D. Payne, Martim Carbone, Monirul I. Sharif,...
VRML
2009
ACM
15 years 11 months ago
Interactive stories on the net: a model and an architecture for X3D worlds
This work discusses a model and an architecture for interactive stories to be displayed on the net, designed for being independent from the specific story represented and suitabl...
Efrem Carnielli, Fabio Pittarello
SBCCI
2005
ACM
123views VLSI» more  SBCCI 2005»
15 years 10 months ago
Fault tolerance overhead in network-on-chip flow control schemes
Flow control mechanisms in Network-on-Chip (NoC) architectures are critical for fast packet propagation across the network and for low idling of network resources. Buffer manageme...
Antonio Pullini, Federico Angiolini, Davide Bertoz...
CASES
2004
ACM
15 years 9 months ago
High-level power analysis for on-chip networks
As on-chip networks become prevalent in multiprocessor systemson-a-chip and multi-core processors, they will be an integral part of the design flow of such systems. With power in...
Noel Eisley, Li-Shiuan Peh