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DAC
2000
ACM
14 years 10 months ago
Performance analysis and optimization of latency insensitive systems
Latency insensitive design has been recently proposed in literature as a way to design complex digital systems, whose functional behavior is robust with respect to arbitrary varia...
Luca P. Carloni, Alberto L. Sangiovanni-Vincentell...
CODES
2006
IEEE
14 years 3 months ago
System-level power-performance trade-offs in bus matrix communication architecture synthesis
System-on-chip communication architectures have a significant impact on the performance and power consumption of modern multiprocessor system-on-chips (MPSoCs). However, customiza...
Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi,...
ICPP
2005
IEEE
14 years 2 months ago
Integrated Performance Monitoring of a Cosmology Application on Leading HEC Platforms
The Cosmic Microwave Background (CMB) is an exquisitely sensitive probe of the fundamental parameters of cosmology. Extracting this information is computationally intensive, requi...
Julian Borrill, Jonathan Carter, Leonid Oliker, Da...
NOCS
2009
IEEE
14 years 3 months ago
Scalability of network-on-chip communication architecture for 3-D meshes
Design Constraints imposed by global interconnect delays as well as limitations in integration of disparate technologies make 3-D chip stacks an enticing technology solution for m...
Awet Yemane Weldezion, Matt Grange, Dinesh Pamunuw...
PDPTA
2000
13 years 10 months ago
Fast Communication Mechanisms in Coarse-grained Dynamically Reconfigurable Array Architectures
The paper focuses on coarse-grained dynamically reconfigurable array architectures promising performance and flexibility for different challenging application areas, e. g. future ...
Jürgen Becker, Manfred Glesner, Ahmad Alsolai...