71 search results - page 6 / 15 » Performance Analysis with High-Level Languages for High-Perf... |
FDL
2003
IEEE
14 years 26 days ago
2003
IEEE
Reconfigurable Systolic Arrays are a generalization of Systolic Arrays where node operations and interconnections can be redefined even at run time. This flexibility increases the...
HPCC
2007
Springer
14 years 1 months ago
2007
Springer
One of the outcomes of DARPA’s HPCS program has been the creation of three new high productivity languages: Chapel, Fortress, and X10. While these languages have introduced impro...
ERSA
2006
13 years 9 months ago
2006
Reconfigurable supercomputing (RSC) combines programmable logic chips with high performance microprocessors, all communicating over a high bandwidth, low latency interconnection n...
ICCV
2011
IEEE
12 years 7 months ago
2011
IEEE
This paper presents a novel approach to utilizing high level knowledge for the problem of scene recognition in an active vision framework, which we call active scene recognition. ...
PROCEDIA
2010
13 years 2 months ago
2010
High performance computing with low cost machines becomes a reality with GPU. Unfortunately, high performances are achieved when the programmer exploits the architectural specific...