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ISCA
2002
IEEE
93views Hardware» more  ISCA 2002»
14 years 3 months ago
Transient-Fault Recovery Using Simultaneous Multithreading
We propose a scheme for transient-fault recovery called Simultaneously and Redundantly Threaded processors with Recovery (SRTR) that enhances a previously proposed scheme for tran...
T. N. Vijaykumar, Irith Pomeranz, Karl Cheng
SCAM
2008
IEEE
14 years 4 months ago
Parfait - A Scalable Bug Checker for C Code
Parfait is a bug checker of C code that has been designed to address developers’ requirements of scalability (support millions of lines of code in a reasonable amount of time), ...
Cristina Cifuentes
SP
2008
IEEE
144views Security Privacy» more  SP 2008»
14 years 4 months ago
Cloaker: Hardware Supported Rootkit Concealment
Rootkits are used by malicious attackers who desire to run software on a compromised machine without being detected. They have become stealthier over the years as a consequence of...
Francis M. David, Ellick Chan, Jeffrey C. Carlyle,...
GLVLSI
2005
IEEE
85views VLSI» more  GLVLSI 2005»
14 years 3 months ago
Utilizing don't care states in SAT-based bounded sequential problems
Boolean Satisfiability (SAT) solvers are popular engines used throughout the verification world. Bounded sequential problems such as bounded model checking and bounded sequentia...
Sean Safarpour, Görschwin Fey, Andreas G. Ven...
DATE
2009
IEEE
144views Hardware» more  DATE 2009»
14 years 4 months ago
Accelerating FPGA-based emulation of quasi-cyclic LDPC codes with vector processing
—FPGAs are widely used for evaluating the error-floor performance of LDPC (low-density parity check) codes. We propose a scalable vector decoder for FPGA-based implementation of...
Xiaoheng Chen, Jingyu Kang, Shu Lin, Venkatesh Ake...