472 search results - page 31 / 95 » Performance Evaluation of Memory Caches in Multiprocessors |
HPCA
2000
IEEE
13 years 12 months ago
2000
IEEE
This paper explores area/parallelism tradeo s in the design of distributed shared-memory (DSM) multiprocessors built out of large single-chip computing nodes. In this context, are...
IPCCC
2007
IEEE
14 years 1 months ago
2007
IEEE
As Chip Multiprocessor (CMP) has become the mainstream in processor architectures, Intel and AMD have introduced their dual-core processors to the PC market. In this paper, perfor...
ICPP
2005
IEEE
14 years 1 months ago
2005
IEEE
In this paper, we present a hierarchical Data Cache Architecture called DCA to effectively slash local interconnect traffic and thus boost the storage server performance. DCA is ...
ISCA
1994
IEEE
13 years 11 months ago
1994
IEEE
This paper evaluates the tradeoffs involved in the design of the software-extended memory system of Alewife, a multiprocessor architecturethat implements coherentsharedmemorythrou...
ISCA
1998
IEEE
13 years 11 months ago
1998
IEEE
Modern cache designs exploit spatial locality by fetching large blocks of data called cache lines on a cache miss. Subsequent references to words within the same cache line result...