472 search results - page 39 / 95 » Performance Evaluation of Memory Caches in Multiprocessors |
HPCA
2001
IEEE
14 years 8 months ago
2001
IEEE
In this papel; we address the severe performance gap caused by high processor clock rates and slow DRAM accesses. We show that even with an aggressive, next-generation memory syst...
JPDC
2007
13 years 7 months ago
2007
Achieving high performance for concurrent applications on modern multiprocessors remains challenging. Many programmers avoid locking to improve performance, while others replace l...
PPOPP
1993
ACM
13 years 11 months ago
1993
ACM
This paper discusses some of the issues involved in implementing a shared-address space programming model on large-scale, distributed-memory multiprocessors. While such a programm...
IPPS
2000
IEEE
13 years 12 months ago
2000
IEEE
The Simultaneous Optical Multiprocessor Exchange Bus (SOME-Bus) is a low-latency, high-bandwidth interconnection network which directly links arbitrary pairs of processor nodes wit...
SIGMETRICS
1996
ACM
13 years 11 months ago
1996
ACM
This paper describes Embra, a simulator for the processors, caches, and memory systems of uniprocessors and cache-coherent multiprocessors. When running as part of the SimOS simul...