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» Performance Evaluation of Memory Caches in Multiprocessors
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MICRO
2007
IEEE
129views Hardware» more  MICRO 2007»
14 years 3 months ago
A Framework for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy
Current on-chip block-centric memory hierarchies exploit access patterns at the fine-grain scale of small blocks. Several recently proposed techniques for coherence traffic reduct...
Jason Zebchuk, Elham Safi, Andreas Moshovos
PODC
1994
ACM
14 years 26 days ago
A Performance Evaluation of Lock-Free Synchronization Protocols
In this paper, we investigate the practical performance of lock-free techniques that provide synchronization on shared-memory multiprocessors. Our goal is to provide a technique t...
Anthony LaMarca
SBACPAD
2003
IEEE
135views Hardware» more  SBACPAD 2003»
14 years 2 months ago
Adaptive Compressed Caching: Design and Implementation
In this paper, we reevaluate the use of adaptive compressed caching to improve system performance through the reduction of accesses to the backing stores. We propose a new adaptab...
Rodrigo S. de Castro, Alair Pereira do Lago, Dilma...
DAMON
2007
Springer
14 years 3 months ago
Parallel buffers for chip multiprocessors
Chip multiprocessors (CMPs) present new opportunities for improving database performance on large queries. Because CMPs often share execution, cache, or bandwidth resources among ...
John Cieslewicz, Kenneth A. Ross, Ioannis Giannaka...
DAMON
2008
Springer
13 years 10 months ago
Data partitioning on chip multiprocessors
Partitioning is a key database task. In this paper we explore partitioning performance on a chip multiprocessor (CMP) that provides a relatively high degree of on-chip thread-leve...
John Cieslewicz, Kenneth A. Ross