472 search results - page 83 / 95 » Performance Evaluation of Memory Caches in Multiprocessors |
ISPDC
2010
IEEE
13 years 6 months ago
2010
IEEE
—Super-scalar, out-of-order processors that can have tens of read and write requests in the execution window place significant demands on Memory Level Parallelism (MLP). Multi- ...
LCPC
2004
Springer
14 years 26 days ago
2004
Springer
Abstract. This paper describes performance of OSCAR multigrain parallelizing compiler on various SMP servers, such as IBM pSeries 690, Sun Fire V880, Sun Ultra 80, NEC TX7/i6010 an...
HPCA
1998
IEEE
13 years 11 months ago
1998
IEEE
The explosive growth in the performance of microprocessors and networks has created a new opportunity to reduce the latency of fine-grain communication. Microprocessor clock speed...
HPCA
2011
IEEE
12 years 11 months ago
2011
IEEE
Future CMPs will combine many simple cores with deep cache hierarchies. With more cores, cache resources per core are fewer, and must be shared carefully to avoid poor utilization...
NOCS
2009
IEEE
14 years 2 months ago
2009
IEEE
While NoCs are efficient in delivering high throughput point-to-point traffic, their multi-hop operation is too slow for latency sensitive signals. In addition, NoCS are inefficie...