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» Performance Evaluation of Memory Caches in Multiprocessors
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CIKM
2006
Springer
13 years 11 months ago
Cache-oblivious nested-loop joins
We propose to adapt the newly emerged cache-oblivious model to relational query processing. Our goal is to automatically achieve an overall performance comparable to that of fine-...
Bingsheng He, Qiong Luo
CF
2009
ACM
14 years 2 months ago
Mapping the LU decomposition on a many-core architecture: challenges and solutions
Recently, multi-core architectures with alternative memory subsystem designs have emerged. Instead of using hardwaremanaged cache hierarchies, they employ software-managed embedde...
Ioannis E. Venetis, Guang R. Gao
ICML
2005
IEEE
14 years 8 months ago
Large scale genomic sequence SVM classifiers
In genomic sequence analysis tasks like splice site recognition or promoter identification, large amounts of training sequences are available, and indeed needed to achieve suffici...
Bernhard Schölkopf, Gunnar Rätsch, S&oum...
MICRO
2006
IEEE
135views Hardware» more  MICRO 2006»
14 years 1 months ago
Support for High-Frequency Streaming in CMPs
As the industry moves toward larger-scale chip multiprocessors, the need to parallelize applications grows. High inter-thread communication delays, exacerbated by over-stressed hi...
Ram Rangan, Neil Vachharajani, Adam Stoler, Guilhe...
IPPS
2003
IEEE
14 years 23 days ago
Simulation of Dynamic Data Replication Strategies in Data Grids
Data Grids provide geographically distributed resources for large-scale data-intensive applications that generate large data sets. However, ensuring efficient access to such huge...
Houda Lamehamedi, Zujun Shentu, Boleslaw K. Szyman...