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MICRO
2010
IEEE
153views Hardware» more  MICRO 2010»
13 years 5 months ago
Throughput-Effective On-Chip Networks for Manycore Accelerators
As the number of cores and threads in manycore compute accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network des...
Ali Bakhoda, John Kim, Tor M. Aamodt
ASPLOS
2004
ACM
14 years 27 days ago
Devirtualizable virtual machines enabling general, single-node, online maintenance
Maintenance is the dominant source of downtime at high availability sites. Unfortunately, the dominant mechanism for reducing this downtime, cluster rolling upgrade, has two short...
David E. Lowell, Yasushi Saito, Eileen J. Samberg
ICS
2005
Tsinghua U.
14 years 29 days ago
Lightweight reference affinity analysis
Previous studies have shown that array regrouping and structure splitting significantly improve data locality. The most effective technique relies on profiling every access to eve...
Xipeng Shen, Yaoqing Gao, Chen Ding, Roch Archamba...
IPPS
2007
IEEE
14 years 1 months ago
Determining the Minimum Energy Consumption using Dynamic Voltage and Frequency Scaling
While improving raw performance is of primary interest to most users of high-performance computers, energy consumption also is a critical concern. Some microprocessors allow volta...
Min Yeol Lim, Vincent W. Freeh
ICS
2003
Tsinghua U.
14 years 20 days ago
Estimating cache misses and locality using stack distances
Cache behavior modeling is an important part of modern optimizing compilers. In this paper we present a method to estimate the number of cache misses, at compile time, using a mac...
Calin Cascaval, David A. Padua