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RTAS
2010
IEEE
13 years 7 months ago
DARTS: Techniques and Tools for Predictably Fast Memory Using Integrated Data Allocation and Real-Time Task Scheduling
—Hardware-managed caches introduce large amounts of timing variability, complicating real-time system design. One alternative is a memory system with scratchpad memories which im...
Sangyeol Kang, Alexander G. Dean
CVPR
2007
IEEE
14 years 10 months ago
In Situ Evaluation of Tracking Algorithms Using Time Reversed Chains
Automatic evaluation of visual tracking algorithms in the absence of ground truth is a very challenging and important problem. In the context of online appearance modeling, there ...
Hao Wu, Aswin C. Sankaranarayanan, Rama Chellappa
EUROSYS
2008
ACM
14 years 5 months ago
Samurai: protecting critical data in unsafe languages
Programs written in type-unsafe languages such as C and C++ incur costly memory errors that result in corrupted data structures, program crashes, and incorrect results. We present...
Karthik Pattabiraman, Vinod Grover, Benjamin G. Zo...
MM
1997
ACM
112views Multimedia» more  MM 1997»
14 years 26 days ago
An Evaluation of VBR Disk Admission Algorithms for Continuous Media File Servers
In this paper, we address the problem of choosing a disk admission algorithm for continuous media streams where each stream may have a di erent bit rate, and more importantly, whe...
Dwight J. Makaroff, Gerald W. Neufeld, Norman C. H...
DSD
2009
IEEE
136views Hardware» more  DSD 2009»
14 years 17 days ago
An Evaluation of Behaviors of S-NUCA CMPs Running Scientific Workload
Modern systems are able to put two or more processors on the same die (Chip Multiprocessors, CMP), each with its private caches, while the last level caches can be either private ...
Pierfrancesco Foglia, Francesco Panicucci, Cosimo ...