Sciweavers

903 search results - page 73 / 181
» Performance Evaluation of a Grid Computing Architecture Usin...
Sort
View
NDSS
2008
IEEE
14 years 2 months ago
Automatic Protocol Format Reverse Engineering through Context-Aware Monitored Execution
Protocol reverse engineering has often been a manual process that is considered time-consuming, tedious and error-prone. To address this limitation, a number of solutions have rec...
Zhiqiang Lin, Xuxian Jiang, Dongyan Xu, Xiangyu Zh...
NOCS
2007
IEEE
14 years 2 months ago
Implementation and Evaluation of a Dynamically Routed Processor Operand Network
— Microarchitecturally integrated on-chip networks, or micronets, are candidates to replace busses for processor component interconnect in future processor designs. For micronets...
Paul Gratz, Karthikeyan Sankaralingam, Heather Han...
TOMACS
1998
140views more  TOMACS 1998»
13 years 7 months ago
Technical Note: A Hierarchical Computer Architecture Design and Simulation Environment
architectures at multiple levels of abstraction, encompassing both hardware and software. It has five modes of operation (Design, Model Validation, Build Simulation, Simulate Syste...
Paul S. Coe, Fred W. Howell, Roland N. Ibbett, Lau...
RTCSA
2006
IEEE
14 years 1 months ago
Systematic Security and Timeliness Tradeoffs in Real-Time Embedded Systems
Real-time embedded systems are increasingly being networked. In distributed real-time embedded applications, e.g., electric grid management and command and control applications, i...
Kyoung-Don Kang, Sang Hyuk Son
ICAC
2007
IEEE
14 years 2 months ago
Time-Sharing Parallel Applications with Performance Isolation and Control
Most parallel machines, such as clusters, are spaceshared in order to isolate batch parallel applications from each other and optimize their performance. However, this leads to lo...
Bin Lin, Ananth I. Sundararaj, Peter A. Dinda