481 search results - page 54 / 97 » Performance Modeling and Measurement of Parallelized Code fo... |
SIGGRAPH
2000
ACM
14 years 1 months ago
2000
ACM
Pomegranate is a parallel hardware architecture for polygon rendering that provides scalable input bandwidth, triangle rate, pixel rate, texture memory and display bandwidth while...
EUROSYS
2007
ACM
14 years 5 months ago
2007
ACM
Software transactional memory (STM) is a promising technique for controlling concurrency in modern multi-processor architectures. STM aims to be more scalable than explicit coarse...
WSC
1998
13 years 10 months ago
1998
We have taken a NIST molecular dynamics simulation program (md3), which was configured as a single sequential process running on a CRAY C90 vector supercomputer, and parallelized ...
PPOPP
2009
ACM
14 years 3 months ago
2009
ACM
Abstract. Transactional memory (TM) promises to simplify construction of parallel applications by allowing programmers to reason about interactions between concurrently executing c...
FPL
2010
Springer
13 years 6 months ago
2010
Springer
FPGA devices are mostly utilized for customized application designs with heavily pipelined and aggressively parallel computations. However, little focus is normally given to the FP...