481 search results - page 56 / 97 » Performance Modeling and Measurement of Parallelized Code fo... |
IPPS
2005
IEEE
14 years 2 months ago
2005
IEEE
Abstract— We developed an automated environment to measure the memory access behavior of applications on high performance clusters. Code optimization for processor caches is cruc...
SPAA
2010
ACM
14 years 1 months ago
2010
ACM
Transactional memory (TM) has shown potential to simplify the task of writing concurrent programs. Inspired by classical work on databases, formal definitions of the semantics of...
ICPP
2002
IEEE
14 years 1 months ago
2002
IEEE
Power aware computing has become popular recently and many techniques have been proposed to manage the energy consumption for traditional real-time applications. We have previousl...
IEEEPACT
2008
IEEE
14 years 3 months ago
2008
IEEE
Chip Multiprocessors (CMPs) allow different applications to concurrently execute on a single chip. When applications with differing demands for memory compete for a shared cache, ...
IPPS
2010
IEEE
13 years 6 months ago
2010
IEEE
Transactional memory is an alternative programming model for managing contention in accessing shared in-memory data objects. Distributed transactional memory (TM) promises to alle...