481 search results - page 62 / 97 » Performance Modeling and Measurement of Parallelized Code fo... |
IEEEPACT
2002
IEEE
14 years 1 months ago
2002
IEEE
Many modern embedded processors (esp. DSPs) support partitioned memory banks (also called X-Y memory or dual bank memory) along with parallel load/store instructions to achieve co...
ICS
1999
Tsinghua U.
14 years 1 months ago
1999
Tsinghua U.
The Virtual Interface (VI) Architecture provides protected userlevel communication with high delivered bandwidth and low permessage latency, particularly for small messages. The V...
IEEEPACT
2008
IEEE
14 years 3 months ago
2008
IEEE
Moore’s Law and the drive towards performance efficiency have led to the on-chip integration of general-purpose cores with special-purpose accelerators. Pangaea is a heterogeneo...
LCPC
2007
Springer
14 years 2 months ago
2007
Springer
Abstract. Partitioned Global Address Space (PGAS) languages offer an attractive, high-productivity programming model for programming large-scale parallel machines. PGAS languages, ...
PDP
2010
IEEE
14 years 3 months ago
2010
IEEE
—This work presents a study undertaken to characterise the behaviour of some parallelisation techniques for irregular codes, previously developed for SMP architectures, on a seve...