Cache hierarchies have been traditionally designed for usage by a single application, thread or core. As multi-threaded (MT) and multi-core (CMP) platform architectures emerge and...
Hyperthreaded (HT) and simultaneous multithreaded (SMT) processors are now available in commodity workstations and servers. This technology is designed to increase throughput by e...
Software DSM systems su er from the high communication and coherence-induced overheads that limit performance. This paper introduces our e orts in reducing system overheads of a h...
This paper presents a model for instruction-level distributed computing that allows the implementation of scalable chip multiprocessors. Based on explicit microthreading it serves ...
Many performance problems observed in high end systems are actually caused by the runtime system and not the application code. Detecting these cases will require parallel performa...
Rashawn L. Knapp, Karen L. Karavanic, Douglas M. P...