481 search results - page 65 / 97 » Performance Modeling and Measurement of Parallelized Code fo... |
ICS
2004
Tsinghua U.
14 years 2 months ago
2004
Tsinghua U.
Cache hierarchies have been traditionally designed for usage by a single application, thread or core. As multi-threaded (MT) and multi-core (CMP) platform architectures emerge and...
IPPS
2005
IEEE
14 years 2 months ago
2005
IEEE
Hyperthreaded (HT) and simultaneous multithreaded (SMT) processors are now available in commodity workstations and servers. This technology is designed to increase throughput by e...
IPPS
1999
IEEE
14 years 1 months ago
1999
IEEE
Software DSM systems su er from the high communication and coherence-induced overheads that limit performance. This paper introduces our e orts in reducing system overheads of a h...
SAMOS
2004
Springer
14 years 2 months ago
2004
Springer
This paper presents a model for instruction-level distributed computing that allows the implementation of scalable chip multiprocessors. Based on explicit microthreading it serves ...
IPPS
2007
IEEE
14 years 3 months ago
2007
IEEE
Many performance problems observed in high end systems are actually caused by the runtime system and not the application code. Detecting these cases will require parallel performa...