This paper considers additive factorial hidden Markov models, an extension to HMMs where the state factors into multiple independent chains, and the output is an additive function...
We address the problem of performance and power-efficient thread allocation in a CMP. To that end, based on analytical model, we introduce a parameterized performance/power metric ...
Abstract. In the field of HPC, the current hardware trend is to design multiprocessor architectures that feature heterogeneous technologies such as specialized coprocessors (e.g., ...
A concept of linearly graded statistical models for analogue performance evaluation is proposed and a suitable technique for automatic generation of analogue performance models us...
This paper presents a model for simultaneous instruction selection, compaction, and register allocation. An arc mapping model along with logical propositions is used to create an ...