260 search results - page 20 / 52 » Performance Modelling and Optimization of Memory Access on C... |
ASPLOS
2010
ACM
14 years 12 days ago
2010
ACM
Heterogeneous computing combines general purpose CPUs with accelerators to efficiently execute both sequential control-intensive and data-parallel phases of applications. Existin...
SIES
2008
IEEE
14 years 1 months ago
2008
IEEE
—Chip multiprocessing design is an emerging trend for embedded systems. In this paper, we introduce a Java multiprocessor system-on-chip called JopCMP. It is a symmetric shared-m...
HPCA
1999
IEEE
13 years 12 months ago
1999
IEEE
Impulse is a new memory system architecture that adds two important features to a traditional memory controller. First, Impulse supports application-specific optimizations through...
WCNC
2008
IEEE
14 years 1 months ago
2008
IEEE
Packet reservation multiple access (PRMA) protocol is an implicit reservation MAC protocol. It is initially designed for voice packets in the cellular networks [2], [3] but it is...
HPCA
2002
IEEE
14 years 8 months ago
2002
IEEE
The increasing performance gap between processors and memory will force future architectures to devote significant resources towards removing and hiding memory latency. The two ma...