Sciweavers

260 search results - page 28 / 52
» Performance Modelling and Optimization of Memory Access on C...
Sort
View
DAC
2012
ACM
11 years 10 months ago
WCET-centric partial instruction cache locking
Caches play an important role in embedded systems by bridging the performance gap between high speed processors and slow memory. At the same time, caches introduce imprecision in ...
Huping Ding, Yun Liang, Tulika Mitra
SC
2005
ACM
14 years 1 months ago
Making Sequential Consistency Practical in Titanium
The memory consistency model in parallel programming controls the order in which operations performed by one thread may be observed by another. Language designers have been reluct...
Amir Kamil, Jimmy Su, Katherine A. Yelick
IEEEPACT
2006
IEEE
14 years 1 months ago
Whole-program optimization of global variable layout
On machines with high-performance processors, the memory system continues to be a performance bottleneck. Compilers insert prefetch operations and reorder data accesses to improve...
Nathaniel McIntosh, Sandya Mannarswamy, Robert Hun...
DAC
2006
ACM
14 years 1 months ago
Signature-based workload estimation for mobile 3D graphics
Until recently, most 3D graphics applications had been regarded as too computationally intensive for devices other than desktop computers and gaming consoles. This notion is rapid...
Bren Mochocki, Kanishka Lahiri, Srihari Cadambi, X...
HPCA
1998
IEEE
13 years 12 months ago
Performance Study of a Concurrent Multithreaded Processor
The performance of a concurrent multithreaded architectural model, called superthreading 15 , is studied in this paper. It tries to integrate optimizing compilation techniques and...
Jenn-Yuan Tsai, Zhenzhen Jiang, Eric Ness, Pen-Chu...