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» Performance Modelling of the Computational Hardware: A Stati...
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130
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ISCA
1992
IEEE
123views Hardware» more  ISCA 1992»
15 years 8 months ago
The Impact of Communication Locality on Large-Scale Multiprocessor Performance
As multiprocessor sizes scale and computer architects turn to interconnection networks with non-uniform communication latencies, the lure of exploiting communication locality to i...
Kirk L. Johnson
137
Voted
ISQED
2007
IEEE
128views Hardware» more  ISQED 2007»
15 years 11 months ago
A Model for Timing Errors in Processors with Parameter Variation
Parameter variation in integrated circuits causes sections of a chip to be slower than others. To prevent any resulting timing errors, designers have traditionally designed for th...
Smruti R. Sarangi, Brian Greskamp, Josep Torrellas
ISVLSI
2005
IEEE
169views VLSI» more  ISVLSI 2005»
15 years 10 months ago
High Performance Array Processor for Video Decoding
high NRE cost. Therefore, general purpose programmable processors using software to perform various functions become more attractive since programmability can simplify system devel...
J. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin
CCGRID
2006
IEEE
15 years 10 months ago
VODCA: View-Oriented, Distributed, Cluster-Based Approach to Parallel Computing
This paper presents a high-performance Distributed Shared Memory system called VODCA, which supports a novel View-Oriented Parallel Programming on cluster computers. One advantage...
Zhiyi Huang, Wenguang Chen, Martin K. Purvis, Weim...
ICS
2010
Tsinghua U.
15 years 9 months ago
Overlapping communication and computation by using a hybrid MPI/SMPSs approach
– Communication overhead is one of the dominant factors that affect performance in high-performance computing systems. To reduce the negative impact of communication, programmers...
Vladimir Marjanovic, Jesús Labarta, Eduard ...